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SimpleMachines enters AI chip race with a design that runs all your models at the same time

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SimpleMachines enters AI chip race with a design that runs all your models at the same time

Simple Machines Inc. (SMI) is in the early stages of producing a processor that speeds AI operations such as speech and language processing and image detection—key operations in biometric identification. SMI aims to stand apart from competitors by enabling customers to simultaneously run all those operations (and more), potentially providing better accuracy and performance in biometric applications

SMI’s claims that a unique programmable architecture for the chip, dubbed Mozart, can simultaneously run a wide range of AI and ML algorithms while offering the performance of purpose-built processors.

“The chip’s design can support very large models today and is capable of running up to 64 different models simultaneously,” said Greg Wright, SMI’s chief architect.  Executives said that initial tests of sample production chips have shown “significant” performance gains across a range of AI applications, unlike specialized AI chips which are built to accelerate a single application such as motion detection or facial recognition.

Future generations of the chip will be offered in everything ranging from enterprise-class high-performance systems to 5-watt IoT devices. The next iteration of the chip, due out in 2021, is expected to offer 20 times the performance of the current generation.

Market research company Omdia forecasts that global AI edge chipset revenue will grow from $7.7 billion in 2019 to $51.9 billion by 2025. Edge inference has emerged as a key workload and many companies have introduced chipset solutions to accelerate AI workloads.

As with most chip design startups, an experienced executive team is crucial to success. SMI’s team is led by founder, CEO and CTO Karu Sankaralingam, a computer science professor at University of Wisconsin-Madison who led the research team that forms the basis for SMI’s design. Other key executives who will be responsible for the design and manufacturing of the chip hail from Qualcomm, Intel and Sun Microsystems.

At the heart of the chip is an approach to chip architecture that the company describes as “Composable Computing,” which translates software application into a small number of defined behaviors. SMI’s software is able to reconfigure the hardware on the fly, with the result being that they chip “behaves as if it were originally designed for that application,” the company said in a statement.

The chip also includes a helping of a high-performance memory interface called High Bandwidth Memory (HBM) that can move the huge volumes of data in and out of the processor faster than other types of dynamic RAM (DRAM) by stacking memory together in a single package. To date, HBM has mostly been seen in supercomputer applications.

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